`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/17 14:46:25
// Design Name: 
// Module Name: Tri2pc_gen
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 根据输入的 fdma_wirq 触发信号 ，产生一个规定时长（LAST_TIME）的脉冲信号，以确保上位机可以采到此信号变化
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Tri2pc_gen#(
    parameter   LAST_TIME   =   32'd10          //10 us
)(
    input           clk       ,
    input           rstn      ,

    input           fdma_wirq ,
    input [7:0]     wbuf_sync ,

    output          Tti_wirq
);

localparam  LAST_CNT = (LAST_TIME*300)-32'd1;




reg fdma_wirq_r1    ;
reg fdma_wirq_r2    ;

always @(posedge clk ) begin
    fdma_wirq_r1 <= fdma_wirq;
    fdma_wirq_r2 <= fdma_wirq_r1;
end

reg [63:0] last_cnt   ;
reg        Tti_wirq_r ;
reg [7:0]  state      ;

always @(posedge clk ) begin
    if(~rstn) begin
        last_cnt <= 64'd0;
        Tti_wirq_r<= 1'b0;
        state     <= 8'd0;
    end
    else begin 
        case (state)
        8'd0: begin
            if({fdma_wirq_r1,fdma_wirq_r2}==2'b10)begin
                state       <= 8'd1;
            end
            else begin
                last_cnt    <= 64'd0;
                Tti_wirq_r  <= 1'b0 ;
                state       <= 8'd0;            
            end
        end
        8'd1: begin
            if(last_cnt >= LAST_CNT) begin
                last_cnt    <= 64'd0;
                Tti_wirq_r  <= 1'b0 ;
                state       <= 8'd0 ; 
            end
            else begin
                last_cnt    <= last_cnt + 1'b1;
                Tti_wirq_r  <= 1'b1 ;
                state       <= 8'd1 ; 
            end
        end
        // 8'd2: begin
            
        // end
            default: state     <= 8'd0;
        endcase
    end
end

assign Tti_wirq  = Tti_wirq_r ;

endmodule
